The present invention relates to field-effect transistors. More specifically, the present invention relates to field-effect transistors with self-aligned carbon nanotube gates.
Transistor scaling over the past few decades has brought about some benefits in terms of device performance and effective cost. For example, the transistor operating frequency (e.g., cut-off frequency) can be increased by scaling down the gate/channel length, which satisfies the demand of making transistors that can be operated at high frequency for various applications.
Due to lithography process limitations, reducing a gate length in a field effect transistor down to the size of a few nanometers can present a challenge. Dimensional limits control the size of circuit elements used in a semiconductor chip, and thus how many circuits can be formed in a given amount of real estate (circuit density). This in turn affects the cost of integrated circuits as well as the speed at which the circuits can operate and how much power is needed to operate an integrated device.